The present invention relates broadly to the field of combining analog and digital signal processing, and more specifically, to an analog-to-digital (A/D) converter of the successive ranging type which comprises apparatus for expanding the performance of a digital-to-analog (D/A) converter included therein; and apparatus for dynamically calibrating the internal offsets of the various range conversion paths as well as the overall offset of the A/D converter over time and temperature variations.
Modern day high performance radar receivers and processors generally include successive ranging type analog-to-digital converters (A/D) with increasing dynamic range and accuracy requirements to assist in the detection and tracking of small targets in the presence of large clutter and larger targets. Since it is generally understood that the ultimate A/D converter transfer characteristics can be no better than the transfer characteristics of the digital-to-analog converter included therein, techniques for expanding the performance of this digital-to-analog converter (D/A) to meet the specifications of the present high performance airborne radars is believed of paramount importance. In addition, most successive ranging type A/D converters encounter troublesome offset errors generally between subranging conversion paths. Presently, these A/D converter offsets may be eliminated by adjustment at a plurality of separate calibration locations at some point in time and temperature. However, these separate calibrations appear to be ineffective to correct for component value drifts dynamically occurring over time and temperature which have a tendency to produce drifting offsets between the conversion paths. Present approaches like a-priori predictions, for example, have attempted to resolve the offset drift phenomenon, but only over limited dynamic performance ranges of the A/D converter. What appears to be needed is an active calibration approach which could eliminate the necessity of cumbersome individual calibration points and correct for offset drifts over a wider dynamic performance range of the A/D converter.
For a better understanding of the aforementioned problems, a description of a typical successive ranging A/D converter, like the one shown schematically in the block diagram embodiment of FIG. 1, will be provided. This particular A/D converter embodiment includes a feedback path with a conventional D/A converter included therein and first and second conversion paths with a subranging gain element included in the second conversion path. In more detail then, referring to FIG. 1, an analog signal 20 is input to a conventional sample and hold circuit 22, the output of which is coupled to the input of a typical unity gain type buffer amplifier 24. The output of amplifier 24 is coupled over a first conversion path 26 to the first position of a conventional single pole double throw analog switch 28 and is also coupled over a second conversion path 30 to the second position of the analog switch 28.
Included in the second conversion path is an adder circuit 32 in cascade with a typical non-inverting amplifier 34 which may be adjusted to a predetermined channel gain. The pole connection of the analog switch 28 may be coupled to a basic A/D converter 36 which for the present embodiment is of the flash converter variety resolving the analog input signal into four bits of binary code provided over its output lines 38. The lines 38 are parallel coupled to the inputs of two storage registers SR1 and SR2. The output of storage register SR1 is fed back to the second conversion path 30 through a conventional D/A converter 40 via line 42 into the negative input of the summer 32 wherein it is subtracted from the analog input signal from the amplifier 24.
In the present embodiment, the outputs of the registers SR1 and SR2 are overlapped in an addition operation performed by a conventional 4-bit adder 44 such that the most significant bit of the SR2 output is added to the least significant bit of the SR1 output. The resulting 7-bit output word is provided over signal lines shown at 50.
In operation then, the input analog signal at 20 is sampled and held for a predetermined time by the circuit at 22. During this predetermined hold time, the analog input signal 20 is buffered by the amplifier 24 and provided to the two conversion paths 26 and 30. The analog switch 28 is first switched to position 1 to allow the basic A/D 36 to convert the analog signal provided over the first conversion path 26 to a 4-bit digital code which is coupled over lines 38 to register SR1. The register SR1 stores the contents of the first conversion until the second conversion is performed and the composite output word at 50 is formed. The first conversion 4-bit word is provided back to the summer 32 via D/A converter 40 and line 42. In the summer 32, the fed back analog signal is subtracted from the input analog signal to provide an error signal .epsilon. in the conversion path 30 which is multiplied by the gain of the amplifier 34 and provided to switch position 2 of 28. The analog switch 28 is then switched to position 2 to allow the basic A/D converter 36 to convert the amplified signal of the second channel 30 into another 4-bit code which is provided to the shift register SR2. The results of the two conversions stored in the shift registers SR1 and SR2, respectively, are added with the aforementioned one bit overlap in the adder 44 to derive the 7-bit output word at 50.
Because of the one bit overlap, the 4-bit code of the register SR1 is merely shifted three bits upward or, in other words, multiplied by 8. Thus, the error .epsilon. formed at the summer 32 will be within 8 quanta (q) wherein 1 quanta is the analog value represented by one least significant bit of the 7-bit output word at 50. In order to bring this error .epsilon. quantity to half-scale range of the basic A/D converter 36, as is generally the case, it may be amplified by a channel gain of 8 in the amplifier 34 as shown in FIG. 1.
It is understood that the use of 4 bits for the conversions resulting in a 7-bit output word was provided hereabove for reasons of simplifying the description of operation of the exemplified embodiment. In general, it is expected that the conversions may be performed with the resolution of 8 bits with the more probable formation of a 14 or 15-bit output word. In these cases, then, the D/A converter 40 will be an 8-bit converter, and in addition, the gain in amplifier 34 of the second conversion path may be increased to 64 or even possibly 128.
Concentrating now on the performance of the D/A converter, in particular, a functional representation of a typical D/A converter with a current output is shown in block 56 of FIG. 2. The current I.sub.D/A provided over the output line 58 from the converter 56 is the analog equivalent of a digital signal 60 provided to the inputs thereof. However, it should be understood that linearity errors in the transfer characteristics of a D/A converter typically may occur as the input code over signal line 60 passes through the transition of one of the more significant bit changes (i.e. 01111111.fwdarw.10000000, for example), due to the fact that a proportionally small error in a more significant bit can cause non-linearities of a size comparable to the least significant bit (LSB) of the converter.
A typical illustration of this phenomenon is shown in the waveform 3A of FIG. 3. For example, as the input digital code over lines 60 to the converter 56 passes through the transition of its most significant bit (MSB) (i.e. the midpoint of the transfer characteristic), it may exhibit the non-linearity as shown in the waveform 3A. In this example, the D/A non-linearity produces an error of 2 quanta, denoted by 2Q, through the code transition between (N/2)-1 and N/2, where N is the highest digital code obtainable over the digital lines 60.
It is understood that additional non-linearities may also exit in the transfer characteristic of the D/A converter during the second MSB transition which occurs at approximately 1/4-scale intervals, and even the third MSB or fourth MSB transitions and so on down the line. However, since an error on the order of one LSB in the MSB represents (1/2.sup.n-1).times.100% of the MSB size, but represents (1/2.sup.n-2).times.100% of the second MSB size, wherein n equals total number of bits in the digital code, it can be shown that the required bit accuracy becomes less stringent as the transition bit becomes less significant. Consequently, non-linearity of an "off-the-shelf" N-bit D/A converter may usually be corrected externally to within the desired specifications by trimming only the most significant bits, rather than all the bits or all of the 2.sup.n code levels.
In the examples exhibited in FIGS. 2 and 3, the non-linearity error of the most significant bit may be compensated for by introducing a trim current at the time when the MSB becomes a "one". One known simple way of adjusting the trim current, denoted in FIG. 2 as I.sub.TRIM, is by way of a potentiometer 62 which has its wiper arm 64 coupled to a conventional current source 66. The output of the current source 66 is coupled to a summing junction 68 through a single-pole-single-throw analog switch 70 which is controlled by the MSB of the digital code 60. As illustrated by the waveform 3B of FIG. 3, the potentiometer 62 may be adjusted to provide a trim current proportional to -2 quanta (-2Q) which may be subtracted from the converter current I.sub.D/A at the summing junction 68 when the MSB of the digital code 60 is activated. The resulting output current, denoted by I.sub.out, then will exhibit no substantial linearity error through the transition of the MSB as illustrated by the waveform 3C of FIG. 3. While this appears to be an adequate solution, this simple permanent adjustment is not capable of tracking the drift of the various components of the D/A converter which may produce non-linearities over any reasonable operational temperature range and even possibly in time. Evidently, some type of dynamic trimming of the D/A converter is needed to track and compensate for these drift errors with time and temperature.
Referring now to the offset drift errors between the conversion paths of a successive ranging A/D converter, any drift in component values occurring up to the output of the buffer amplifier 24 generally appears only as a drift in overall input offset. However offset drifts occurring along both conversion paths in an uncorrelated relationship may cause the level of the second conversion range to shift away from its ideal 1/4 to 3/4 scale centered range setting with respect to the conversion range of the basic A/D converter 36. Now if this offset drift becomes enough to throw the second conversion range either below or above scale, say, -1/4 to 1/4 scale or 3/4 to 11/4 scale, for example, then the basic A/D converter 36 may not provide accurate conversions in those regions exceeding its possible conversion range, and repetitive discontinuities in the transfer characteristics thereof may result.
Typical offset drifts of the conversion paths may occur in the analog switch 28, the analog amplifier 34, the summer 32 and even the input circuitry of the basic A/D converter 36. In fact, any offset not appearing equally in both conversion paths 26 and 30 may throw the second conversion range off scale wherein, as previously stated, repetitive discontinuities will occur. Moreover, while the control of the subrange offset drift appears essential, the control of the overall offset drive is also desirable to maintain full dynamic range of the overall A/D converter system as well as to provide a controllable characteristic where prospective problem areas due to the successive ranging process are predictable. Accordingly, tightly controlled offset drift appears very important if the direct-coupled characteristics of the A/D converter are to be repeatable. Offset drifts occurring both in the subrange paths and in the input sample-and-hold and buffer circuits 22 and 24, respectively, may effect the overall A/D conversion accuracy.